1. Field of the Invention
This invention relates generally to data communications in a computer system. In particular, the invention relates to a timestamp logic circuit which precisely positions packets for a queue based memory controller.
2. Description of Related Art
Computer systems rely heavily upon Dynamic Random Access Memories (xe2x80x9cDRAMsxe2x80x9d) to implement system memories due to their simplicity, affordability and memory density. However, it is increasingly difficult to design memory systems that satisfy the size and performance requirements for modem computer systems using DRAMs connected by conventional bus architectures. To overcome these limitations, a memory subsystem can be constructed using a memory channel architecture. Intelligent memory devices are connected by a narrow, high-speed bus, termed a channel. Packets of information are used to communicate between the memory controller and the memory devices. Direct Rambus(trademark) architecture using a Direct Rambus(trademark) Memory Controller and a Rambus(copyright) memory channel is an example of a memory subsystem using a memory channel architecture. The Direct Rambus(trademark) architecture provides for a maximum of 32 Rambus DRAM (RDRAM(copyright)) devices on a Rambus(copyright) memory channel with a maximum of 128 megabytes (MB) per RDRAM(copyright) and 4 gigabytes (GB) on the channel. The Rambus(copyright) memory channel operates at data rates up to 800 megahertz (MHz).
The Direct Rambus(trademark) Memory Controller (hereinafter memory controller) is a block of digital logic residing on an Application Specific Integrated Circuit (ASIC) and manages the memory transactions of the Rambus(copyright) memory system. The memory controller connects through a Rambus(copyright) ASIC Cell (RAC) to the Rambus(copyright) memory channel (hereinafter memory channel) and the RDRAMs. The RAC provides an interface between the memory controller and the memory channel to convert the low-swing voltage levels used by the memory channel to the CMOS logic levels internal to the ASIC and vice-versa. The memory controller operates at 100 MHz whereas the memory channel operates at 400 MHz such that there are four memory channel clock cycles (termed a slot) for every memory controller clock cycle. The memory channel operates at 400 MHz but data is transferred on both the rising and falling edges of each clock cycle such that the data transfer rate on to the memory channel is 800 MHz.
The memory controller sends command packets across the memory channel to the RDRAMs for performing read and write transactions. The memory controller has a queue with a plurality of queue positions and includes packet scheduling logic to schedule times for the packets in the various positions of the queue. The memory controller needs to schedule times for packets based upon timing constraints between different packets. The timing constraints require that certain packets be spaced apart from one another in the queue by a specified amount of time to insure the proper operation of the read and write transactions. Presently, in order to schedule a packet, the memory controller must position a packet on the first clock cycle of the slot""s four memory channel clock cycles. Unfortunately, oftentimes the next time a packet can be scheduled, immediately after a timing constraint, falls after the first clock cycle of the slot such that the packet must be positioned at the beginning of the next following slot wasting memory channel clock cycles.
One embodiment of the present invention is a method comprising assigning times for each queue position of a queue. Some of the queue positions have a packet scheduled at a scheduled time. Bubbles are added to the queue positions to adjust the scheduled time for the packet to precisely position the packet.